
`include "defines.v"

//----------------------------------------------------------------
//Module Name : EXMEM_reg.v
//Description of module:
//
//----------------------------------------------------------------
//Designer:	Tang Pengyu
//Date: 2021/9/28/08:43  
//----------------------------------------------------------------
module	EXMEM_reg(
	input	clk,
	input	exmem_rst,
	input	exmem_ena,
//from if
	input	[`INST_ADDR_LEN-1:0]	i_ififif_pc_out,		//regfile
	input	i_ififif_fetched,								//regfile
//	input	i_ififif_time_intr_r,					//wb
	input	[`INST_ADDR_LEN-1:0] i_ififif_addr,
	
//from id
	input	i_idid_rs1_r_ena,				//--csr_reg,regfile
	input	[4:0]	i_idid_rs1_r_addr,	//--csr_reg,regfile
	input	i_idid_rs2_r_ena,				//--regfile
	input	[4:0]	i_idid_rs2_r_addr,	//--regfile
	input	i_idid_rd_w_ena,				//--csr_reg,regfile
	input	[4:0]	i_idid_rd_w_addr,		//--csr_reg,regfile
	input	[`REG_DATA_LEN-1:0] i_idid_op2,	//reg	
	input	[7:0]	i_idid_inst_opcode,
//from	ctrlid
	input	[1:0]	i_ctrlidctrlid_wb_sel,			//regfile
	input	i_ctrlidctrlid_ecall_en,					//wb
	input	i_ctrlidctrlid_mret_en,					//wb
	
//from exe
	input	[`REG_DATA_LEN-1:0]	i_exe_data,		//--WB
//from CSR_UNIT
	input	[11:0]	i_csrunit_csr_addr,		//wb
	input	i_csrunit_csr_w_ena,			//wb
	input	[`REG_DATA_LEN-1:0]	i_csrunit_csr_w_data,		//wb
	input	i_csrunit_csr_r_ena,			//wb
	input	[63:0]	i_csrunit_csr_r_data,
//from ctrlexe
	input	i_ctrlexe_load_axi_en,			//regfile
	input	i_ctrlexe_load_clint_en,		//regfile
	input	i_ctrlexe_store_axi_en,		
	input	i_ctrlexe_store_clint_en,
//	input	i_ctrlexe_wb_sel,				//regfile
//from clint
	input	[63:0]	i_clint_load_data,
	
	output	reg [`INST_ADDR_LEN-1:0]	o_ififif_pc_out,
	output	reg o_ififif_fetched,
//	output	reg o_ififif_time_intr_r,
	output	reg [`INST_ADDR_LEN-1:0] o_ififif_addr,
	
	output	reg o_idid_rs1_r_ena,				//--csr_reg,regfile
	output	reg [4:0]	o_idid_rs1_r_addr,	//--csr_reg,regfile
	output	reg o_idid_rs2_r_ena,				//--regfile
	output	reg [4:0]	o_idid_rs2_r_addr,	//--regfile
	output	reg o_idid_rd_w_ena,				//--csr_reg,regfile
	output	reg [4:0]	o_idid_rd_w_addr,		//--csr_reg,regfile	
	output	reg	[`REG_DATA_LEN-1:0] o_idid_op2,
	output	reg [7:0]	o_idid_inst_opcode,
	
	output	reg	[1:0]	o_ctrlidctrlid_wb_sel,
	output	reg o_ctrlidctrlid_ecall_en,
	output	reg o_ctrlidctrlid_mret_en,
	
	output	reg [`REG_DATA_LEN-1:0]	o_exe_data,
	
	output	reg [11:0]	o_csrunit_csr_addr,
	output	reg o_csrunit_csr_w_ena,
	output	reg [`REG_DATA_LEN-1:0]	o_csrunit_csr_w_data,
	output	reg o_csrunit_csr_r_ena,
	output	reg	[63:0]	o_csrunit_csr_r_data,
	
	output	reg o_ctrlexe_load_axi_en,
	output	reg o_ctrlexe_load_clint_en,
	output	reg o_ctrlexe_store_axi_en,
	output	reg o_ctrlexe_store_clint_en,
//	output	reg o_ctrlexe_wb_sel

	output	reg [63:0]	o_clint_load_data
	
);

always @(posedge clk)	begin
	if(exmem_rst)	begin
		o_ififif_pc_out <= {`INST_ADDR_LEN{1'b0}};
		o_ififif_fetched <= 1'b0;
//		o_ififif_time_intr_r <= 1'b0;
		o_ififif_addr <= {`INST_ADDR_LEN{1'b0}};

		o_idid_rs1_r_ena <= 1'b0;
		o_idid_rs1_r_addr <= 5'd0;
		o_idid_rs2_r_ena <= 1'b0;
		o_idid_rs2_r_addr <= 5'd0;
		o_idid_rd_w_ena <= 1'b0;
		o_idid_rd_w_addr <= 5'd0;
		o_idid_op2 <= {`REG_DATA_LEN{1'b0}};
		o_idid_inst_opcode <= 8'b000_00100;
	
		o_ctrlidctrlid_wb_sel <= 2'b00;
		o_ctrlidctrlid_ecall_en <= 1'b0;
		o_ctrlidctrlid_mret_en <= 1'b0;
	
		o_exe_data <= {`REG_DATA_LEN{1'b0}};
	
		o_csrunit_csr_addr <= 12'd0;
		o_csrunit_csr_w_ena <= 1'b0;
		o_csrunit_csr_w_data <= {`REG_DATA_LEN{1'b0}};
		o_csrunit_csr_r_ena <= 1'b0;
		o_csrunit_csr_r_data <= 64'd0;
	
		o_ctrlexe_load_axi_en <= 1'b0;
		o_ctrlexe_load_clint_en <= 1'b0;
		o_ctrlexe_store_axi_en <= 1'b0;
		o_ctrlexe_store_clint_en <= 1'b0;
		
		o_clint_load_data <= 64'd0;
	end
	else if(exmem_ena)	begin
		o_ififif_pc_out <= i_ififif_pc_out;
		o_ififif_fetched <= i_ififif_fetched;
//		o_ififif_time_intr_r <= i_ififif_time_intr_r;
		o_ififif_addr <= i_ififif_addr;

		o_idid_rs1_r_ena <= i_idid_rs1_r_ena;
		o_idid_rs1_r_addr <= i_idid_rs1_r_addr;
		o_idid_rs2_r_ena <= i_idid_rs2_r_ena;
		o_idid_rs2_r_addr <= i_idid_rs2_r_addr;
		o_idid_rd_w_ena <= i_idid_rd_w_ena;
		o_idid_rd_w_addr <= i_idid_rd_w_addr;
		o_idid_op2 <= i_idid_op2;
		o_idid_inst_opcode <= i_idid_inst_opcode;
	
		o_ctrlidctrlid_wb_sel <= i_ctrlidctrlid_wb_sel;
		o_ctrlidctrlid_ecall_en <= i_ctrlidctrlid_ecall_en;
		o_ctrlidctrlid_mret_en <= i_ctrlidctrlid_mret_en;
	
		o_exe_data <= i_exe_data;
	
		o_csrunit_csr_addr <= i_csrunit_csr_addr;
		o_csrunit_csr_w_ena <= i_csrunit_csr_w_ena;
		o_csrunit_csr_w_data <= i_csrunit_csr_w_data;
		o_csrunit_csr_r_ena <= i_csrunit_csr_r_ena;
		o_csrunit_csr_r_data <= i_csrunit_csr_r_data;
	
		o_ctrlexe_load_axi_en <= i_ctrlexe_load_axi_en;
		o_ctrlexe_load_clint_en <= i_ctrlexe_load_clint_en;
		o_ctrlexe_store_axi_en <= i_ctrlexe_store_axi_en;
		o_ctrlexe_store_clint_en <= i_ctrlexe_store_clint_en;	
		
		o_clint_load_data <= i_clint_load_data;
	
	
	end

end

endmodule